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never stop thinking. isoface tm ISO1H815G coreless transformer isolated digital output 8 channel 1.2a high-side switch datasheet , version 2.0, july 2009 power management & drives
ISO1H815G : : ( )
type on-state resistance package ISO1H815G 200m pg-dso-36 datasheet 3 version 2.0, 2009-07-28 isoface tm ISO1H815G coreless transformer isolated digital output 8 channel 1.2a high-side switch product highlights ? coreless transformer i solated data interface galvanic isolation 8 high-side output switches 1,2a c compatible 8-bit parallel peripheral ISO1H815G c (i.e c166) ad0 wr p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p1.x vcc vcc parallel interface control unit ct control & protectio n unit cs wr d0 d1 d2 d3 d4 d5 d6 d7 dis vcc gndcc gndbb gnd out7 vbb vbb out1 out0 typical application diag diag isolated return pat h for diag signal features ? interface 3.3/5v cmos operation compatible parallel interface direct control mode high common mode transient immunity short circuit protection maximum current internally limited overload protection overvoltage protection (including load dump) undervoltage shutdown with autorestart and hysteresis switching inductive loads common output disable pin thermal shutdown with restart thermal independence of separate channels common diagnostic output for overtemperature esd protection loss of gndbb and loss of v bb protection reverse output voltage protection rohs compliant typical application isolated switch for indust rial applications (plc) all types of resistive, inductive and capacitive loads c compatible power switch for 24v dc applications driver for solenoid, relays and resistive loads description the ISO1H815G is a galvanically isolated 8 bit data interface in pg-dso-36 package that provides 8 fully protected high-side power switches that are able to handle currents up to 1.2a. an 8 bit parallel c compat ible interfac e allows to connect the ic directly to a c system. the input interface supports also a direct control mode and is designed to operate with 3.3/5v cmos compatible levels. the data transfer from input to output side is realized by the integrated coreless transformer technology.
isoface tm ISO1H815G pin configuration and functionality datasheet 4 version 2.0, 2009-07-28 1 pin configuration and functionality 1.1 pin configuration pin symbol function 1 n.c. not connected 2 vcc positive 3.3/5v logic supply 3 dis output disable 4 cs chip select 5 wr parallel write 6 d0 data input bit0 7 d1 data input bit1 8 d2 data input bit2 9 d3 data input bit3 10 d4 data input bit4 11 d5 data input bit5 12 d6 data input bit6 13 d7 data input bit7 14 diag common diagnostic output for overtemperature 15 gndcc input logic ground 16 n.c. not connected 17 n.c. not connected 18 n.c. not connected 19 gndbb output driver ground 20 n.c not connected 21 out7 high-side output of channel 7 22 out7 high-side output of channel 7 23 out6 high-side output of channel 6 24 out6 high-side output of channel 6 25 out5 high-side output of channel 5 26 out5 high-side output of channel 5 27 out4 high-side output of channel 4 28 out4 high-side output of channel 4 29 out3 high-side output of channel 3 30 out3 high-side output of channel 3 31 out2 high-side output of channel 2 32 out2 high-side output of channel 2 33 out1 high-side output of channel 1 34 out1 high-side output of channel 1 35 out0 high-side output of channel 0 36 out0 high-side output of channel 0 tab vbb positive driver power supply voltage vcc d1 1 dis cs wr 5 4 2 3 d3 d5 d2 d4 d0 6 7 8 9 10 d6 11 d7 12 diag 13 gndcc 14 15 n.c. 16 17 18 36 32 33 35 34 31 30 29 28 27 26 25 24 23 22 21 20 19 out0 out2 out0 out1 out1 out3 out4 out3 out4 out2 out5 out5 out6 out6 gndbb out7 out7 n.c. n.c. n.c. n.c. vbb vbb tab tab figure 1 power so-36 (430mil) .
datasheet 5 version 2.0, 2009-07-28 isoface tm ISO1H815G pin configuration and functionality 1.2 pin functionality vcc (positive 3.3/5v logic supply) the vcc supplies the input interface that is galvanically isolated from the output driver stage. the input interface can be supplied with 3.3/5v. dis (output disable) the high-side outputs out0...out7 can be immediately switched off by means of the low active pin ',6 that is an asynchronous signal. the input registers are also reset by the ',6 signal. the output remains switched off after low-high transition of dis signal, till new information is written into the input register. current sink to gndcc. &6 (chip select) the system microcontroller selects the ISO1H815G by means of the low active pin &6 to activate the parallel interface. by connecting the &6 pin and :5 pin to ground the parallel direct control is activated. current source to vcc. :5 (parallel write) in parallel mode data at the input pins (d0 ... d7) are latched by means of the rising edge of the low active signal :5 (write). current source to vcc. d0 ... d7 (data input bit0 ... bit7) the present data can be latched on the rising edge of the write signal :5 . d0 ... d7 control the corresponding output channels out0 ...out7. by connecting cs and :5 to ground, the signals at d0 ... d7 directly control the outputs. current sink to gndcc. ',$* (common diagnostic output for overtemperature) the low active ',$* signal contains the or-wired information of the separated overtemperature detection units for each channel.the output pin ',$* provides an open drain functionality. a current source is also connected to the pin ',$* . in normal operation the signal ',$* is high. when overtemperature or vbb below on-limit is detected the signal ',$* changes to low. gndcc (ground for vcc domain) this pin acts as the ground reference for the input interface that is supplied by vcc. gndbb (output driver ground domain) this pin acts as the ground reference for the output driver that is supplied by vbb. out0 ... out7 (high side output channel 0 ... 7) the output high side channels are internally connected to vbb and controlled by the corresponding data input pins d0 ... d7 in parallel mode. tab (vbb, positive supply for output driver) the heatslug is connected to the positive supply port of the output interface.
datasheet 6 version 2.0, 2009-07-28 isoface tm ISO1H815G blockdiagram 2blockdiagram parallel input interface < d0 - d7 > d1 d2 d3 d4 d5 d6 d7 d0 wr cs overvoltage protection undervoltage shutdown with restart voltage source common diagnostic output serial to parallel to logic channel 1 - 6 temperature sensor out0 overload protection current limitation limitation of unclamped inductive load logic charge pump level shifter rectifier high-side channel 0 temperature sensor out7 overload protection current limitation limitation of unclamped inductive load logic charge pump level shifter rectifier high-side channel 7 channel 1 ... 6 from temperature sensor channel 1 - 6 to logic channel 1 - 6 vbb logic undervoltage shutdown with restart vbb gndbb vcc gndcc galvanic isolation dis out1 out2 out3 out4 out5 out6 gate protection gate protection ISO1H815G direct mode control diag parallel to serial ct 100a vcc figure 2 blockdiagram
isoface tm ISO1H815G functional description datasheet 7 version 2.0, 2009-07-28 3 functional description 3.1 introduction the isoface ISO1H815G includes 8 high-side power switches that are controlled by means of the integrated parallel interface. the interface is 8bit c compatible. furthermore a direct control mode can be selected that allows the direct control of the outputs out0...out7 by means of the inputs d0...d7 without any additional logic signal. the ic can replace 8 optocouplers and the 8 high-side switches in conventional i/o-applications as a galvanic isolation is implemented by means of the integrated coreless transformer technology. the c compatible interfac es allow a direct connection to the ports of a microcontroller without the need for other components. each of the 8 high-side power switches is protected against short to vbb, overload, overtemperature and against overvoltage by an active zener clamp. the diagnostic logic on the power chip recognizes the overtemperature information of each power transistor the information is send via the in ternal coreless transformer to the pin diag at the input interface. 3.2 power supply the ic contains 2 galvanic isolated voltage domains that are independent from each other. the input interface is supplied at vcc and the output stage is supplied at vbb. the different voltage domains can be switched on at different time. the output stage is only enabled once the input stage enters a stable state. 3.3 output stage each channel contains a high-side vertical power fet that is protected by embedded protection functions. the continuous current for each channel is 1.2a (all channels on). 3.3.1 output stage control each output is independently controlled by an output latch and a common reset line via the pin dis that disables all eight outputs and reset the latches. the parallel input data is transferred to the input latches with a high-to-low transition of the signal wr (write) while the cs is logic low. a low-to-high transition of cs transfers then the data of the input latches to the output buffer. 3.3.2 power transistor overvoltage protection each of the eight output stages has it own zener clamp that causes a voltage limitation at the power transistor when solenoid loads are switched off. v on is then clamped to 47v (min.). vz vbb gndbb outx v on vbb figure 3 inductive and overvoltage output clamp (each channel) energy is stored in the load inductance during an inductive load switch-off. e l 12 ? li l 2 = e l gndbb v bb outx e r l r l e load z l vbb e bb e as dx figure 4 inductive load switch-off energy dissipation (each channel) while demagnetizing the load inductance, the energy dissipation in the dmos is e as e bb e l e r ? v on cl () i l t () dt = + = with an approximate solution for r l > 0 : e as i l l 2r l --------------- - v bb v on cl () + () 1 i l r l v on cl () ------------------------ - + ?? ?? ln = 3.3.3 power transistor overcurrent protection the outputs are provided with a current limitation that enters a repetitive switched mode after an initial peak
datasheet 8 version 2.0, 2009-07-28 isoface tm ISO1H815G functional description current has been exceeded. the initial peak short circuit current limit is set to i l(scp) . during the repetitive mode short circuit current the limit is set to i l(scr) . if this operation leads to an overtemperature condition, a second protection level (t j > 135c) will change the output into a low duty cycle pwm (selective thermal shutdown with restart) to prevent critical chip temperatures. in vout t j t t t t diag figure 5 overtemperatu re detection the following figures show the timing for a turn on into short circuit and a short circ uit in on-state. heating up of the chip may require several milliseconds, depending on external conditions. in vout i l t t t t diag output short to gnd i l(scp) i l(scr) figure 6 turn on into short circuit, shut down by overtemperature, restart by cooling in vout i l t t t t diag output short to gnd i l(scp) i l(scr) normal operation figure 7 short circuit in on-state, shut down down by overtemperature, restart by cooling 3.4 common diagnostic output the overtemperature detection information are or- wired in the common diagnostic output block. the information is send via the integrated coreless transformer to the input interface. the output stage at pin diag has an open drain functionality combined with a current source. common diagnostic output ct 100a vcc diag figure 8 common diagnostic output
datasheet 9 version 2.0, 2009-07-28 isoface tm ISO1H815G functional description 3.5 parallel interface the ISO1H815G contains a parallel interface that can be directly controlled by the microcontroller output ports. the parallel interface can also be switched over to a direct control that allows direct changes of the outputs out0 ... out7 by means of the corresponding inputs d0 ... d7 without additional logic signals. to activate the parallel direct control mode pin cs and pin wr have to be connected both to ground. 3.5.1 parallel interface signal description cs - chip select. the system mi crocontroller selects the ISO1H815G by means of the cs pin. whenever the pin is in a logic low state, data can be transferred from the c. cs parallel input data can be written in from then on cs the data in the input latches is transferred to the output buffer wr - write. the system controller enables the write procedure in the ISO1H815G by means of the signal wr . a logic low state signal at pin wr writes the input data into the input latches when the cs pin is in a logic low state. wr parallel input data at the pi ns d0 - d7 is written into the input latches wr the parallel input data is latched in the input latches. any changes at the pins d0 - d7 after the low-to-high transition of wr do not affect the input latches. d0 ... d7 - parallel input. parallel data bits are fed into the pins d0 ... d7. the data is written into the input latches when wr is logic low. 3.5.2 uc control mode parallel interface ic1 output l i nes c (i.e c166) cs wr ad0 wr number of adressed ics = n number of necessary control and data ports = 9 n individual ics are adressed by the chip select p0 p1 p2 p3 p4 p5 p6 p7 d0 d1 d2 d3 d4 d5 d6 d7 diag figure 9 parallel bus configuration 3.5.3 direct control mode beside the use of the parallel c compatible interface a parallel direct control mode can be choosen. in this mode the output out0...out7 can be directly controlled via the inputs d0...d7 without the need for additional logic signals. to activate this mode pin cs and wr need to be connected to ground. . parallel interface ic1 output l i nes controller p0 p1 p2 p3 p4 p5 p6 p7 d0 d1 d2 d3 d4 d5 d6 d7 vcc vcc vcc cs wr diag figure 10 parallel direct control
datasheet 10 version 2.0, 2009-07-28 isoface tm ISO1H815G functional description 3.6 parallel interface timing cs wr data t whcs t wrpw d0 - d7 t ds t dh t cswr t csd out0 - out7 t on/off output figure 11 parallel input - output timing diagram 3.7 transmission failure detection there is a failure detection unit integrated to ensure also a stable functionality during the integrated coreless transformer transmission. this unit decides wether the transmitted data is valid or not. if four times serial data coming in from the internal registers is not accepted, the output stages are switched off until the next valid data is received.
isoface tm ISO1H815G electrical characteristics datasheet 11 version 2.0, 2009-07-28 4 electrical characteristics note: all voltages at pins 2 to 14 are measured with respect to ground gndcc (pin 15). all voltages at pin 20 to pin 36 and tab are measured with respect to ground gndbb (pin 19). the voltage levels are valid if other ratings are not violated. the two voltage domains v cc and v bb are internally galvanic isolated. 4.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. for the same reason make sure, that any capac itor that will be connected to pin 2 ( v cc) and tab (vbb) is discharged before assembling the application circuit. supply voltages higher than v bb(az) require an external current limit for the gndbb pin, e.g. with a 15 resistor in gndbb connection. operating at absolute maximum ratings can lead to a reduced lifetime. parameter at t j = -40 ... 135c, unless otherwise specified symbol limit values unit min. max. supply voltage input interface (vcc) v cc -0.5 6.5 v supply voltage output interface (vbb) v bb 1) defined by p tot -1 1) 45 continuos voltage at data inputs (d0 ... d7) v dx -0.5 6.5 continuos voltage at pin cs v cs -0.5 6.5 continuos voltage at pin wr v wr -0.5 6.5 continuos voltage at pin dis v dis -0.5 6.5 continuos voltage at pin diag v diag -0.5 6.5 load current (short-circuit current) i l self limited a reverse current through gndbb 1) i gndbb -1.6 operating temperature t j -25 internal limited c storage temperature t stg -50 150 power dissipation 2) device on 50mm*50mm*1.5mm epoxy pcb fr4 with 6cm2 (one la yer, 70m thick) copper area for drain connection. pcb is vertical without blown air. 2) p tot 3.3 w inductive load switch-off energy dissipation 3) not subject to production test, specified by design 3) single pulse, t j = 125c, i l = 1.2a one channel active all channel simultaneously active (each channel) e as 5 0.5 j load dump protection 3) v loaddump 4) v loaddump is setup without the dut connected to the generator per iso7637-1 and din40839 4) =v a + v s v in = low or high t d = 400ms, r i = 2 , r l = 27 , v a = 13.5v t d = 350ms, r i = 2 , r l = 57 , v a = 27v v loaddump 90 117 v electrostatic discharge voltage (human body model) according to jesd22-a114-b v esd 2 kv electrostatic discharge voltage (charge device model) according to esd stm5.3.1 - 1999 v esd 1 kv continuos reverse drain current 1)3) , each channel i s 4 a
datasheet 12 version 2.0, 2009-07-28 isoface tm ISO1H815G electrical characteristics 4.2 thermal characteristics parameter at t j = -25 ... 125c, v bb =15...30v, v cc =3.0...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. thermal resistance junction - case r thjc ? ? 1.5 k/w thermal resistance @ min. footprint r th(ja) ? ? 50 thermal resistance @ 6cm2 cooling area 1) device on 50mm*50mm*1.5mm epoxy pcb fr4 with 6cm2 (one la yer, 70m thick) copper area for drain connection. pcb is vertical without blown air. 1) r th(ja) ? ? 38 4.3 load switching capabi lities and characteristics parameter at t j = -25 ... 125c, v bb =15...30v, v cc =3.0...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. on-state resistance, i l = 0.5a, each channel t j = 25c t j = 125c two parallel channels, t j = 25c: 1) four parallel channels, t j = 25c: 1) r on ? ? 150 270 75 38 200 320 100 50 m ? nominal load current device on pcb 38k/w, t a = 85c, t j < 125c one channel: 1) not subject to production test, specified by design 1) two parallel channels: 1) four parallel channels: 1) i l(nom) 1.4 2.2 4.4 a turn-on time to 90% v 2) the turn-on and turn-off time includes the switching time of the high-side switch and the transmission time via the coreless transformer in normal operating mode. during a failure on the co reless transformer transmission turn-on or turn-off time can increase by up to 50s. out 2) r l = 47 ? , v dx = 0 to 5v t on ? 64 120 s turn-off time to 10% v out 2) r l = 47 ? , v dx = 5 to 0v t off ? 89 170 slew rate on 10 to 30% v out r l = 47 ? , v bb = 15v dv/dt on ? 1 2 v/s slew rate off 70 to 40% v out r l = 47 ? , v bb = 15v -dv/dt off ? 1 2 4.4 operating parameters parameter at t j = -25 ... 125c, v bb =15...30v, v cc =3.0...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. common mode transient immunity 1) ? v iso /dt -25 - 25 kv/s ? v iso = 200v magnetic field immunity 1) h im 100 a/m iec61000-4-8
isoface tm ISO1H815G electrical characteristics datasheet 13 version 2.0, 2009-07-28 voltage domain v bb (output interface) operating voltage v bb 11 35 v undervoltage shutdown v bb(under) 7 10.5 undervoltage restart v bb(u_rst) 11 undervoltage hysteresis v bb(under) 0.5 undervoltage current i bb(uvlo) 1 2.5 ma v bb < 7v operating current i gndl 10 14 ma all channels on - no load leakage output current (included in i bb(off) ) v dx = low, each channel i l(off) 5 30 a voltage domain v cc (input interface) operating voltage v cc 3.0 5.5 v undervoltage shutdown v cc(under) 2.5 2.9 undervoltage restart v cc(u_rst) 3 undervoltage hysteresis v cc(under) 0.1 undervoltage current i cc(uvlo) 1 2 ma v cc < 2.5v operating current i cc(on) 4.5 6 ma 1) not subject to production test
datasheet 14 version 2.0, 2009-07-28 isoface tm ISO1H815G electrical characteristics 4.5 output protection functions parameter 1) integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?out side? normal operating range. protection functions are not designed for continous repetitive operation. 1) at t j = -25 ... 125c, v bb =15...30v, v cc =3.0...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. initial peak short circuit current limit, each channel t j = -25c, v bb = 30v, t m = 700s t j = 25c t j = 125c two parallel channels: 3) four parallel channels: 3) i l(scp) ? ? 1.4 ? 3.0 ? 4.5 ? ? a twice the current of one channel four times the curre nt of one channel repetitive short circuit current limit 3) t j = t jt (see timing diagrams) each channel: two parallel channels: 3) four parallel channels: 3) i l(scr) ? 2.2 2.2 2.2 ? output clamp (inductive load switch off) at v out = v bb - v on(cl) v on(cl) 47 53 60 v overvoltage protection v bb(az) 47 ? ? thermal overload trip temperature 2) higher operating temperature at normal function for each channel available 3) not subject to production test, specified by design 2)3) t jt 135 ? ? c thermal hysteresis 3) ? t jt ? 10 ? k 4.6 diagnostic characteristics at pin diag at t j = -25 ... 125c, v bb =15...30v, v cc =3.0...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. common diagnostic sink current (overtemperature of any channel) t j = 135c i diagsink 5 ma v diagon < 0.25xvcc common diagnostic source current i diagsource 100 a
isoface tm ISO1H815G electrical characteristics datasheet 15 version 2.0, 2009-07-28 4.7 input interface parameter at t j = -25 ... 125c, v bb =15...30v, v cc =3.0...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. input low state voltage (d0 ... d7, dis , cs , wr ) v il -0.3 ? 0.3 x v cc v input high state voltage (d0 ... d7, dis , cs , wr ) v ih 0.7 x v cc ? v cc + 0.3 input voltage hysteresis (d0 ... d7, dis , cs , wr ) v ihys 100 mv input pull down current (d0 ... d7, dis ) i idown 100 a input pull up current ( cs , wr ) -i iup 100 output disable time (transition dis to logic low) 1)2) 1) the time includes the turn-on/off time of the high-side switch and the transmission time via the coreless transformer. 2) if pin dis is set to low the outputs are set to low; after dis set to high a new write cycle is nec essary to set the output again. normal operation turn-off time to 10% v out r l = 47 ? t dis --- 85 170 s output disable time (transition dis to logic low) 3) the parameter is not subject to production test - verified by design/characterization 1)2)3) disturbed operation turn-off time to 10% v out r l = 47 ? t dis --- --- 230 4.8 parallel interface input timing parameter at t j = -25 ... 125c, v bb =15...30v, v cc =3.0...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. wr pulse width t wrpw 20 ? ? ns data setup time before wr t ds 20 ? ? data hold time after wr t dh 10 ? ? chip select valid to wr t cswr 0 ? ? wr logic high to cs logic high t whcs 10 ? ? delay to next cs cycle t csd 10 ? ?
datasheet 16 version 2.0, 2009-07-28 isoface tm ISO1H815G electrical characteristics 4.9 reverse voltage parameter at t j = -25 ... 125c, v bb =15...30v, v cc =3.0...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. reverse voltage 1) defined by p tot 2) not subject to production test, specified by design 1)2) r gnd = 0 ? r gnd = 150 ? -v bb ? ? ? ? 1 45 v diode forward on voltage if = 1.25a, v dx = low, each channel -v on ? ? 1.2 4.10 isolation and safety-related specification parameter measured from input terminals to output terminals, unless otherwise specified value unit conditions rated dielectric isolation voltage v iso 500 v ac 1 - minute duration 1) the parameter is not subject to pro duction test, verified by characterization; production test with 1100v, 100ms duration 1) short term temporary overvoltage 1250 v 5s acc. din en60664-1 1) minimum external air gap (clearance) 2.6 mm shortest distance through air. minimum external tracking (creepage) 2.6 mm shortest distance path along body. minimum internal gap 0.01 mm insulation distance through insulation 4.11 reliability for qualification report please contact your local infineon technologies office!
datasheet 17 version 2.0, 2009-07-28 isoface tm ISO1H815G electrical characteristics
datasheet 18 version 2.0, 2009-07-28 isoface tm ISO1H815G electrical characteristics
isoface tm ISO1H815G package outlines datasheet 19 version 2.0, 2009-07-28 5 package outlines bottom view does not include plastic or metal protrusion of 0.15 max. per side 1 18 0.25 0.1 1.1 36 +0.13 0.25 36x 19 m (heatslug) 15.74 0.65 0.1 c ab 19 c 3.25 3.5 max. +0.1 0 0.1 0.1 36 2.8 b 11 0.15 1) 1.3 5? 0.25 3? -0.02 +0.07 6.3 14.2 (mold) 0.3 b 0.15 0.25 heatslug 0.95 heatslug 0.1 5.9 3.2 (metal) 0.1 (metal) 13.7 (metal) 10 1 -0.2 index marking (mold) 15.9 1) 0.1 a 1 x 45? 1) gps09181_1 pg-dso-36 (plastic dual small outline package) figure 12 pg-dso-36
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